3-30 march 1997 cdp1802ac/3 high-reliability cmos 8-bit microprocessor features ? for use in aerospace, military, and critical industrial equipment ? minimum instruction fetch - execute time of 4.5 m s (maximum clock frequency of 3.6mhz) at v dd = 5v, t a = +25 o c ? operation over the full military temperature range . . . . . . . . . . . . . . . -55 o c to +125 o c ? any combination of standard ram and rom up to 65,536 bytes ? 8Cbit parallel organization with bidirectional data bus and multiplexed address bus ? 16 x 16 matrix of registers for use as multiple pro- gram counters, data pointers, or data registers ? on-chip dma, interrupt, and flag inputs ? high noise immunity . . . . . . . . . . . . . . . . . . 30% of v dd description the cdp1802a/3 high - reliability lsi cmos 8 - bit register oriented central - processing unit (cpu) is designed for use as a general purpose computing or control element in a wide range of stored - program systems or products. the cdp1802a/3 includes all of the circuits required for fetching, interpreting, and executing instructions which have been stored in standard types of memories. extensive input/output (i/o) control features are also provided to facili- tate system design. the 1800 series architecture is designed with emphasis on the total microcomputer system as an integral entity so that systems having maximum ?exibility and minimum cost can be realized. the 1800 series cpu also provides a synchronous interface to memories and external controllers for i/o devices, and minimizes the cost of interface controllers. further, the i/o interface is capable of supporting devices operating in polled, interrupt - driven, or direct memory - access modes. the cdp1802ac/3 is functionally identical to its predeces- sor, the cdp1802. the a version includes some perfor- mance enhancements and can be used as a direct replacement in systems using the cdp1802. this type is supplied in 40 lead dual - in - line sidebrazed ceramic packages (d suf?x). pinout cdp1802ac/3 (SBDIP) top view ordering information package temp. range ( o c) 5v - 3.2mhz pkg no. SBDIP -55 to 125 cdp1802acd3 d40.6 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 clock w ait clear q sc1 sc0 mrd bus 7 bus 6 bus 5 bus 4 bus 3 bus 2 bus 1 bus 0 v cc n2 n1 n0 v ss 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 v dd xt al dma in dma out interr upt mwr tpa tpb ma7 ma6 ma5 ma4 ma3 ma2 ma1 ma0 ef1 ef2 ef3 ef4 file number 1441.2 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. http://www.intersil.com or 407-727-9207 | copyright ? intersil corporation 1999 [ /title (cdp1 802ac / 3) / sub- j ect (high- reli- ability cmos 8-bit micro- proces- sor) / autho r () / key- words (inter- sil corpo- ration, 8-bit micro- proces- sors, 8 bit micro- proces- sors, periph- erals) / cre- ator () / doci nfo pdf- mark
3-31 cdp1852 input port data cs1 cs2 cdp1852 output port clock cs1 cs2 ma0C7 n0 mrd mwr n1 tpb data tpa cdp1802 8Cbit cpu mrd ma0C4 mwr cs cdp1824 32 byte ram ma0C7 data ceo tpa mrd 8Cbit data bus address bus cdp1833 1kCrom data figure 1. typical cdp1802a/3 small microprocessor system cdp1802ac/3
3-32 absolute maximum ratings thermal information dc supply voltage range, (v dd ) (all voltages referenced to v ss terminal) cdp1802ac/3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +7v input voltage range, all inputs . . . . . . . . . . . . . -0.5v to v dd +0.5v dc input current, any one input . . . . . . . . . . . . . . . . . . . . . . . . . 10ma thermal resistance (typical) q ja ( o c/w) q jc ( o c/w) SBDIP package. . . . . . . . . . . . . . . . . . . . 55 15 device dissipation per output transistor t a = full package temperature range. . . . . . . . . . . . . . . . . 100mw operating temperature range (t a ) package type d. . . . . . . . . . . . . . . . . . . . . . . . . .-55 o c to +125 o c storage temperature range (t stg ). . . . . . . . . . . .-65 o c to +150 o c lead temperature (during soldering) at distance 1/16 1/32 in. (1.59 0.79mm) from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . +265 o c caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not im plied. recommended operating conditions t a = full package temperature range. for maximum reliability, operating conditions should be selected so that operation is always within the following ranges parameter min max units dc operating voltage range 4 6.5 v input voltage range v ss v dd v maximum clock input rise or fall time - 1 m s performance speci?cations parameter v dd (v) - 55 o c to +25 o c +125 o c units minimum instruction time (note 1) 5 4.5 5.9 m s maximum dma transfer rate 5 450 340 kbytes/s maximum clock input frequency, load capacitance (c l ) = 50pf, f cl 5 dc-3.6 dc-2.7 mhz note: 1. equals 2 machine cycles - one fetch and one execute operation for all instructions except long branch and long skip, which re quire 3 machine cycles - one fetch and two execute operations. static electrical speci?cations all limits are 100% tested parameter conditions -55 o c, +25 o c +125 o c units v out (v) v in, (v) v cc, v dd (v) min max min max quiescent device current, i dd - - 5 - 100 - 250 m a output low drive (sink) current (except xt al), i ol 0.4 0, 5 5 1.20 - 0.90 - ma xt al 0.4 5 5 185 - 140 - m a output high drive (source) current (except xt al), i oh 4.6 0, 5 5 - -0.30 - -0.20 ma xt al 4.6 0 5 - -135 - -100 m a output voltage low-level, v ol - 0, 5 5 - 0.1 - 0.2 v output voltage high-level, v oh - 0, 5 5 4.9 - 4.8 - v cdp1802ac/3
3-33 input low voltage, v il 0.5, 4.5 - 5 - 1.5 - 1.5 v input high voltage, v ih 0.5, 4.5 - 5 3.5 - 3.5 - v input leakage current, i in any input 0, 5 5 - 1- 5 m a three-state output leakage current, i out 0, 5 0, 5 5 - 1- 5 m a note: 2. 5v level characteristics apply to part no. cdp1802ac/3, and 5v and 10v level characteristics apply to part no. cdp1802a/3. timing speci?cations as a function of t (t = 1/fclock), c l = 50 pf parameter v dd (v) limits (note 3) -55 o c, +25 o c +125 o c units high-order memory-address byte setup to tpa time, t su 5 2t-450 2t-580 ns high-order memory-address byte hold after tpa time, t h 5 t/2 +0 t/2 +0 ns low-order memory-address byte hold after wr time, t h 5 t-30 t-40 ns cpu data to bus hold after wr time, t h 5 t-170 t-250 ns required memory access time address to data, t acc 5 5t-300 5t-400 ns note: 3. these limits are not directly tested. implicit speci?cations (note 4) t a = -55 o c to +25 o c parameter symbol v dd (v) typical values units typical total power dissipation idle 00 at m(0000), c l = 50pf f = 2mhz - 5 4 mw effective input capacitance any input - c in -5pf effective three-state terminal capacitance data bus - - 7.5 pf minimum data retention voltage - v dr - 2.4 v data retention current - i dr 2.4 10 m a note: 4. these specifications are not tested. typical values are provided for guidance only. static electrical speci?cations all limits are 100% tested (continued) parameter conditions -55 o c, +25 o c +125 o c units v out (v) v in, (v) v cc, v dd (v) min max min max cdp1802ac/3
3-34 dynamic electrical speci?cations c l = 50pf, timing measurement at 0.5 v dd point parameters v dd (v) -55 o c to +25 o c +125 o c units min max min max progagation delay times, t plh , t phl clock to tpa, tpb 5 - 275 - 370 ns clock-to-memory high address byte, t plh , t phl 5 - 725 - 950 ns clock-to-memory low address byte valid, t plh , t phl 5 - 340 - 425 ns clock to mrd, t plh , t phl 5 - 340 - 425 ns clock to mwr, t plh , t phl 5 - 275 - 370 ns clock to (cpu data to bus) valid, t plh , t phl 5 - 430 - 550 ns clock to state code, t plh , t phl 5 - 440 - 550 ns clock to q, t plh , t phl 5 - 375 - 475 ns clock to n (0 - 2), t plh , t phl 5 - 400 - 525 ns interface timing requirements (note 5) data bus input setup, t su 5 10 - 10 - ns data bus input hold, t h 5 175 - 230 - ns dma setup, t su 5 10 - 10 - ns dma hold, t h 5 200 - 270 - ns interrupt setup, t su 5 10 - 10 - ns interrupt hold, t h 5 175 - 230 - ns w ait setup, t su 5 30 - 30 - ns ef1-4 setup, t su 5 20 - 20 - ns ef1-4 hold, t h 5 100 - 135 - ns required pulse width times clear pulse width, t wl 5 150 - 200 - ns clock pulse width, t wl 5 140 - 185 - ns note: 5. minimum input setup and hold times required by part cdp1802ac/3. cdp1802ac/3
3-35 notes: 6. this timing diagram is used to show signal relationships only, and does not represent any specific machine cycle. 7. all measurements are referenced to 50% point of the waveforms. 8. shaded areas indicate dont care or undefined state. multiple transitions may occur during this period. figure 2. timing waveforms 0 2 3 4 5 6 7 0 00 10 20 30 40 50 60 70 00 01 11 21 31 41 51 61 71 01 t w clock t plh t phl tpa tpb t su t h t plh t phl t plh, t p h l low order address byte memory address t plh mrd (memory read cycle) t phl t plh t plh t phl t phl mwr (memory write cycle) data from cpu to bus state codes t plh t phl t plh t phl q t plh, t phl n0, n1, n2 (i/o execution cycle) t plh data latched in cpu data from bus to cpu t h dma interrupt sampled (s1, s2) t su t h t su t h dma request interr upt request flag lines sampled (in si) ef 1-4 t su t h w ait clear t w t su any negative transition t plh, t phl t plh t phl sampled (s1, s2, s3) t su 1 high order address byte t plh, t phl t plh, t p h l cdp1802ac/3
3-36 performance curves figure 3. typical maximum clock frequency as a function of temperature figure 4. typical maximum clock frequency as a function of supply voltage figure 5. typical transition time vs load capacitance figure 6. minimum output high (source) current characteristics figure 7. minimum output low (sink) current characteristics notes: 9. idle = 00 at m (0000) 10. branch = 3707 at m (8107) figure 8. typical power dissipation as a function of clock frequency for branch instruction and idle instruction 5 4 3 2 1 0 6 7 8 35 45 55 65 75 85 95 105 115 25 125 system maximum clock frequency (f cl ) (mhz) v dd = 5v load capacitance (c l ) = 50pf ambient temperature (t a ) ( o c) 345678910 12 2 supply voltage (v dd ) (v) 11 5 4 3 2 1 0 6 7 system maximum clock frequency (f cl ) (mhz) 8 load capacitance (c l ) = 50pf t a = 25 o c t a = 125 o c extrapola ted 50 75 100 125 150 175 200 25 300 250 200 150 100 350 400 0 50 transition time (t thl , t tlh ) (ns) ambient temperature (t a ) = 25 o c 0 load capacitance (c l ) (pf) t tlh t thl -9 -8 -7 -6 -5 -4 -3 -10 2 3 4 5 6 1 0 -2 -1 output high (source) current (i oh -ma) drain to source voltage (v ds ) (v) gate to source voltage (v gs ) = -5v ambient temperature = -40 to +85 o c 0 25 20 15 10 5 30 35 123456 7 08910 gate to source voltage (v gs ) = 5v ambient temperature = -40 o c to +85 o c output low (sink) current (i ol ) (ma) 0 drain-to-source voltage (v ds ) (v) 10 1 0.1 100 1000 0.01 0.1 1 10 ambient temperature (t a ) = 25 o c clock input frequency (f cl ) (mhz) typical power dissipation (p d ) (mw) v cc = v dd = +5v v cc = v dd = 5v branch idle cdp1802ac/3
3-37 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/o r speci?cations at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of p atents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see web site http://www.intersil.com burn-in circuit note: any output except xt al. figure 9. typical change in propagation delay as a function of a change in load capacitance type v dd temperature time cdp1802ac 7v +125 o c 160 hours figure 10. bias/static burn-in circuit performance curves (continued) 100 75 50 25 0 125 150 d propagation delay time ( d t plh , d t phl ) (ns) 50 100 150 200 0 d load capacitance ( d c l ) (pf) ambient temperature (t a ) = 25 o c v cc = v dd = 5v d t phl d t plh v cc = v dd = 5v v dd v dd nc nc v dd v dd nc 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 all resistors are 47k w 20% cdp1802ac/3
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